Eda solutions for double patterning lithography semantic scholar. Double patterning and hypernumerical aperture immersion lithography mark amirtharaj zach kruder enee416 111711. Selfaligned double patterning, part one design with calibre. May 24, 2018 renwick believes that the competition between lowna euv double patterning and 193i quad patterning will be similar to the current situation i. Request pdf singlemask doublepatterning lithography this paper proposes shifttrim double patterning lithography stdpl, a costeffective method for achieving 2. Lithography experts report on advanced multiple patterning. We present experimental and simulation results from investigating critical issues challenging double patterning lithography capability to meet manufacturing requirements for 45 nm 12 pitch on 0. Pdf assessing chiplevel impact of double patterning. Lithoetchlithoetch lele and selfaligned double patterning sadp. Dp requires that the dense circuit patterns be partitioned into two separate exposures, which decreases the pattern densities in each exposure and. Double patterning lithography dpl is one of the most likely shortterm solutions for keeping the pace of scaling beyond 32nm node 2. Assessing chiplevel impact of double patterninglithography. Note that we have made no attempt to include everything, or even everything which is important in dfm.
Triple patterning and selfaligned double patterning sadp sphere. In this book, we have aimed to present the most stateoftheart research results on dfm with multiple patterning lithography mpl and electron beam lithography ebl. In order to achieve this, some version of double patterning dp technol ogy will need to be combined with established techniques. Abstractin double patterning lithography dpl layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors corresponding to different exposures if their spacing is less than the minimum coloring spacing. Lithography and other patterning techniques for future. Dpt poses unique demands on critical dimension cd uniformity and overlay control, making the tolerance decrease much faster than the rate at which. This affects the complexity of the design process and the performance, variability and density of the resultant devices. Although the cost of ownership of a combined method is an issue, the huge opportunity costs of any ngl in its current state make dp lithography dpl. He detailed a patterning process that consisted of immersion single exposure to the 38 nm halfpitch hp, with selfaligned double patterning sadp down to the 19 nm hp, and selfaligned quadruple patterning saqp to the 9. By assigning different values to a and b, the pdf takes a variety. Triple patterning and selfaligned double patterning sadp.
Design for manufacturability with advanced lithography. Simulations of lithography alternatives for positive and negative patterning processes based on focusexposure metrics. Self aligned double patterning is another pitch doubling technique, interesting for onedimensional designs on narrow pitches. Pdf effective decomposition algorithm for selfaligned. Preferred embodiment methods of the invention are executed by a computer and provide alternate methods for layout decomposition for double patterning lithography dpl using integer linear programming ilp. Multiple patterning or multi patterning is a class of technologies for manufacturing integrated circuits ics, developed for photolithography to enhance the feature density. Among different dpl techniques lithoetchlithoetch lele and selfaligned double. Next to it, alternative, more cost effective dp approaches are discussed. Pdf double patterning technology friendly detailed routing.
Alignment method of selfaligned double patterning process. As a practical solution, pitch doubling technique known as double patterning lithography dpl has become a strong candidate for 22nm. Selfaligned double patterning developed in response to leles mask overlay issues single lithography step need to use an additional block or cut mask to remove unwanted material complicated to design masks for sadp process intensive c. As double patterning lithography dpl becomes the leading candidate for sub30 nm lithography process, we need a fast and lithography friendly decomposition framework. The invention provides systems and methods for layout decomposition to produce exposure layouts that can be used to perform double patterning lithography dpl.
As such, double patterning lithography dpl is the most promising option to generate the required lithography resolution, where the target layout is printed with two separate imaging processes. Page 3 complimentary lithography use dipole illumination or alternating psm to form dense linesspaces or sadp for smaller pitch use second lithoetch step to trim ends of lines. Dp requires that the dense circuit patterns be partitioned into two separate exposures, which decreases the pattern densities in each exposure and thus improves resolution and depth of focus dof. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. To compensate, chipmakers are using advanced techniques like double quadruple and spacerbased patterning, involving multiple masks and process sets. The downsides of using double patterning include increased mask reticle and lithography costs, and the imposition of further restrictions on the ways in which circuits can be laid out on chip. Double patterning dpt lithography is seen industrywide as an intermediate solution for the 32nm node if high index immersion as well as extreme ultraviolet lithography are not ready for a timely release for production. Besides the increase of process complexity and costs a further penalty is the introduction of uncorrelated variations between the two incremental lithography steps. To realize double patterning lithography, patterns located within a subresolution dis. For the semiconductor industry, double patterning is the only lithography technique to be used for the 32 nm and 22 nm halfpitch nodes in 20082009 and 20112012, respectively, using tools already available today there are several types of double patterning. A method includes performing a double patterning process to form a first mandrel, a second mandrel, and a third mandrel, with the third mandrel being between the first mandrel and the second mandrel, and etching the third mandrel to cut the third mandrel into a fourth mandrel and a fifth mandrel, with an opening separating the fourth mandrel from the fifth mandrel.
Lecture 59 che 323 lithography double patterning youtube. When i first began working on doublepatterning dp tools back in late 2010, there was already talk that it might be a fruitless, or at a minimum, very shortlived project, as extreme ultraviolet euv lithography was just around the corner and. Double patterning lithography dpl has been considered as a practical solution for manufacturing process. Multiple patterning enables chipmakers to image ic designs at 20nm and below. It will enable designers to develop chips for manufacture on sub30nm process nodes using current optical lithography systems. A number of works have sought to quantify the impact of overlay in double patterning lithography, either analytically or empirically. As a practical solution, pitch doubling technique known as double patterning lithography. Singlemask doublepatterning lithography for reduced cost.
Double patterning dp was originally developed for photolithography to enhance the resolution of imprinted features. Immersion lithography and double patterning in advanced. Simultaneous overlay and cd measurement for double patterning. Eda solutions for double patterning lithography by minoo mirsaeedi athesis presentedtotheuniversityofwaterloo inful. Introduction doublepatterning lithography dpl is one of the most likely. Double patterning and hypernumerical aperture immersion. Dpl can be implemented with different manufacturing processes. Sadp is similar to the lithoetchlithoetch lele double patterning dp youre all coming to grips with in 201614nm technologies, in that it uses two masks to define the final pattern on the wafer. Selfaligned double patterning sadp lithography is a novel lithography technology that has the intrinsic capability to reduce the overlay in the double patterning lithography dpl. Index termsdouble patterning lithography dpl, integer linear programming ilp, layout decomposition, node splitting.
Introduction as moores law continues to drive performance and integration with smaller circuit features, lithography is pushed to new extremes. This document is for information and instruction purposes. When combining this method with double patterning, many of these companies are able to achieve critical dimensions of around 25nm 6. Multiple patterning or multipatterning is a class of technologies for manufacturing integrated circuits ics, developed for photolithography to enhance the feature density. In the absence of euv lithography, the primary option for manufacturing on a 10nm process is to extend double patterning. Even as these approaches ease lithography limitations, they create new demands for exceptional process precision and film quality in order to accurately produce the fine, dense features required. Us8402396b2 layout decomposition for double patterning. Increasing the optical aperture of the optics double patterning techniques the other way is to decrease the wavelength of the light used in patterning. While many resolution enhancement technologies ret have been developed recently, including sourcemask optimization smo1, and pixilated illumination2 schemes for the scanner, the overarching requirement for the light source in double patterning has been a need for improved optical performance stability and higher. Fast and scalable parallel layout decomposition in double. For all technologies, from flint arrowheads to dna microarrays, patterning the functional material is crucial. Double patterning technology friendly detailed routing. Renwick believes that the competition between lowna euv doublepatterning and 193i quadpatterning will be similar to the current situation i. Double patterning for 32nm and beyond linkedin slideshare.
Us10170306b2 method of double patterning lithography. Double patterning is a technique that decomposes a single layout into two masks in order to increase pitch size and improve depth of focus df. Delays in readiness of next generation lithography ngl suggest the use of existing methods to enable the production of key technologies at the 32 and 22nm halfpitch nodes. Layout optimizations for double patterning lithography. Selfaligned double patterning sadp process is one of several dpt approaches, and most likely be introduced into. However, thats the only thing these two technologies have in common. Simultaneous overlay and cd measurement for double. It is one of the many resolution enhancement techniques ret that have been introduced to push the limit of optical lithography. Double, triple and quadruple patterning and future lithography. Double patterning for sub28nm ics tech design forum. As double patterning lithographydpl becomes the leading candidate for sub30 nm lithography process, we need a fast and lithography friendly decomposition framework. At the first lithography step, a photo mask containing only the blue part of the. Among different dpl techniques lithoetchlithoetch lele and self. Double patterning is the only lithography technique to be used for the 32 nm and 22 nm halfpitch nodes in 20082009 and 20112012, respectively, using tools already available today.
Mask characterization for double patterning lithography. Double patterning technology friendly detailed routing minsik cho, yongchan ban, and david z. Stateoftheart 193 nm tool with a numerical aperture of 1. Singlemask doublepatterning lithography request pdf. Double patterning and hypernumerical aperture immersion lithography.
Pdf eda solutions for double patterning lithography. High reliability arf light source for double patterning. Double patterning at 20nm is one of those big unavoidable changes that it is almost impossible to know too much about. These techniques show the capability of immersion lithography and double patterning to scale beyond the 32nm hp node. Double patterning is a technique used in the lithographic process that defines the features of integrated circuits at advanced process nodes. Index termsdouble patterning, shifttrim, photomask, trim exposure, overlay, bimodal cd distribution, manufacturing throughput, mask cost. Given a target layout, lele decomposes layout patterns and assigns them into two masks for two exposure steps. Detailed routing for spacerismetal type selfaligned. The most obvious of these is 193nm immersion 193i lithography. As optical lithography advances to 32 nm technology node and beyond, double patterning technology dpt has emerged as an attractive solution to circumvent the fundamental optical limitations. Advanced multipatterning and hybrid lithography techniques.
Mentor graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in. Detailed routing for spacerismetal type selfaligned double. The basic principle of dp is to print a pattern with dimensions near or below the resolution limit by splitting the pattern into two or more complementary parts which are successively formed on the wafer. It is expected to be necessary for the 10 nm and 7 nm node semiconductor processes and beyond. Key challenges for extending multiple exposures lithography are cost, process complexity, and design issues, especially for random logic. Lithography and other patterning techniques for future electronics abstract. Double patterning is a class of technologies developed for photolithography to enhance the feature density. Industry leaders such as intel, texas instruments, etc. Double patterning in nanoimprint lithography sciencedirect. Double patterning lithography dpl is one of the most likely shortterm solutions for keeping the pace of scaling beyond 32nm node 6. Dpl has become a strong candidate for 22nm lithography process.
Typically, double patterning refers to the lithoetchlithoetch lele pitchsplitting. For semiconductor integrated circuits ics, it is even more critical than for most technologies because enormous benefits accrue to going smaller, notably. Although sadp is the critical technology to solve the lithography. Because quadruple patterning is already in use, our concern in this roadmap is whether multiple patterning will be extended beyond quadruple patterning, rather than can it work in manufacturing. To compensate, chipmakers are using advanced techniques like doublequadruple and spacerbased patterning, involving multiple masks and process sets. Expanding the optical lithography to 32nm node and beyond is impossible using existing single exposure systems. Mentors david abercrombie, dfm program manager for calibre, has written a series of articles detailing the multifaceted impacts of double patterning on advanced node design and verification. Doublepatterning lithography dpl is one of the most likely shortterm solutions for keeping the pace of scaling beyond 32nm node 2. Assessing chiplevel impact of double patterning lithography.
In order to achieve this, some version of double patterning dp technology will need to be combined with established techniques. Pdf double patterning technology dpt is a most likely lithography solution for 3222 nm technology nodes as of 2008 due to the delay of extreme. Doublepatterning lithography dpl is one of the most likely shortterm solutions for keeping the pace of scaling beyond 32nm node 6. Eda solutions for double patterning lithography by minoo mirsaeedi athesis. Double patterning still needs two masks masks are expensive, block mask more so there are additional process steps half of all features are created by a very different process no overlay errors due to selfalignment nonmandrel shapes are not perfect replicas mandrel and nonmandrel shapes have different variations. Double patterning lithography for 32 nm spie digital library. Manufacturing challenges in double patterning lithography. The basic idea is that if a pitch of interest is not achievable in a single lithography step, the design is split over two lithography layers in a way that the minimum pitch. Process sequence for lithoetchlithoetch double patterning. In double patterning, feature sizes are reduced by splitting one mask level into two. Selfaligned double patterning lithography aware detailed routing with color preassignment yixiao ding, student member, ieee, chris chu, fellow, ieee and waikei mak, member, ieee, abstractas the technology nodes scale down to sub22nm, double patterning lithography dpl has been considered as a practical solution for layout manufacturing. As a result, double patterning dp lithography technology has become the most feasible interim solution. Jan 01, 2009 double patterning dpt lithography is seen industrywide as an intermediate solution for the 32nm node if high index immersion as well as extreme ultraviolet lithography are not ready for a timely release for production.
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